Publications
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “On designing via-configurable cell blocks for regular fabrics”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 198 -203.
, “Designing via-configurable logic blocks for regular fabric”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
, “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
, “Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms”, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
, “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
, “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
, “An efficient algorithm for local don't care sets calculation”, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.
, “Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching”, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
, “Efficient circuit clustering for area and power reduction in FPGAs”, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
, “Efficient circuit clustering for area and power reduction in FPGAs”, in FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, 2002, pp. 59–66.
, “Efficient closed-form crosstalk delay metrics”, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
, “Efficient delay calculation in presence of crosstalk”, in Quality Electronic Design, 2000. ISQED 2000. Proceedings. IEEE 2000 First International Symposium on, 2000, pp. 491 -497.
, “An Efficient Mechanism for Performance Optimization of Variable-Latency Designs”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
, “Efficient minimization algorithms for fixed polarity AND/XOR canonical networks”, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
, “Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing”, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
, “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
, “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
, “Efficient static timing analysis in presence of crosstalk”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 335 -339.
, “Electromigration and voltage drop aware power grid optimization for power gated ICs”, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
, “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
, “Eliminating false positives in crosstalk noise analysis”, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
, “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
, “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
, “FAR: fixed-points addition & relaxation based placement”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
