Publications

Found 266 results
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2010
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
V. S. Nandakumar, Newmark, D., Zhan, Y., and Marek-Sadowska, M., “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
2009
J. - Y. Wuu, Pikus, F. G., Torres, A., Marek-Sadowska, M., Singh, V. K., and Rieger, M. L., “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
A. Todri and Marek-Sadowska, M., “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Transistor-level layout of high-density regular circuits”, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Transistor-level layout of high-density regular circuits”, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
2008
N. Modi and Marek-Sadowska, M., “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
N. Modi and Marek-Sadowska, M., “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Fast and simple modeling of non-rectangular transistors”, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
H. Jiang and Marek-Sadowska, M., “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
A. Todri, Marek-Sadowska, M., and Kozhaya, J., “Power supply noise aware workload assignment for multi-core systems”, in Computer-Aided Design, 2008. ICCAD 2008. IEEE/ACM International Conference on, 2008, pp. 330 -337.
A. Todri and Marek-Sadowska, M., “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.

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