Publications

Found 27 results
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S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
L. H. Chen and Marek-Sadowska, M., Closed-Form Crosstalk Noise Delay Metrics, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
L. H. Chen, Marek-Sadowska, M., Divecha, R., and Singh, P., Capturing input switching dependency in crosstalk noise modeling, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., Coping with buffer delay change due to power and ground noise, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
L. H. Chen and Marek-Sadowska, M., Closed-form crosstalk noise metrics for physical design applications, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 812 - 819.
D. I. Cheng, Lin, C. - C., and Marek-Sadowska, M., Circuit partitioning with logic perturbation, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
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S. Grygiel, Perkowski, M., Marek-Sadowska, M., Luba, T., and Jozwiak, L., Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
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M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., Crosstalk minimization for multiple clock tree routing, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., A crosstalk aware two-pin net router, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
B. Hu and Marek-Sadowska, M., Congestion minimization during placement without estimation, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 739 - 745.
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H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
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Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
C. - C. Lin, Lee, T. - C., Marek-Sadowska, M., and Chen, K. - C., Cost-free scan: a low-overhead scan path design methodology, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., Cost-free scan: a low-overhead scan path design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
Q. Liu and Marek-Sadowska, M., A congestion-driven placement framework with local congestion prediction, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
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M. Marek-Sadowska and Sarrafzadeh, M., The crossing distribution problem [IC layout], Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 14, pp. 423 -433, 1995.
M. Marek-Sadowska and Sarrafzadeh, M., The crossing distribution problem, in Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, 1991, pp. 528 -531.
A. Mukherjee and Marek-Sadowska, M., Clock and power gating with timing closure, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
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X. Qiu and Marek-Sadowska, M., Can pin access limit the footprint scaling?, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
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Y. Ran and Marek-Sadowska, M., Crosstalk noise in FPGAs, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
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A. Singh and Marek-Sadowska, M., Circuit clustering using graph coloring, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
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A. Vittal and Marek-Sadowska, M., Crosstalk reduction for VLSI, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Crosstalk in VLSI interconnections, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
A. Vittal, Ha, H., Brewer, F., and Marek-Sadowska, M., Clock skew optimization for ground bounce control, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
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K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.

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