Publications

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Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., Post-layout Logic Restructuring For Performance Optimization, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
A. Singh, Mukherjee, A., Macchiarulo, L., and Marek-Sadowska, M., PITIA: an FPGA for throughput-intensive applications, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Pipelining sequential circuits with wave steering, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
M. Marek-Sadowska and Lin, S., Pin assignment for improved performance in standard cell design, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
S. - C. Chang and Marek-Sadowska, M., Perturb And Simplify: Multi-level Boolean Network Optimizer, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., Perturb and simplify: multilevel Boolean network optimizer, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 1494 -1504, 1996.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Performance study of VeSFET-based, high-density regular circuits, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., Performance Optimization Using Variable-Latency Design Style, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
M. Marek-Sadowska, Pad Assignment for Power Nets in VLSI Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 550 - 560, 1987.
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Y. - L. Wu and Marek-Sadowska, M., Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 568 -573.
W. Maly, Yi-Wei Lin, and Marek-Sadowska, M., OPC-Free and Minimally Irregular IC Design Style, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 954 -957.
K. Wang and Marek-Sadowska, M., On-chip power-supply network optimization using multigrid-based technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
K. Wang and Marek-Sadowska, M., On-chip power supply network optimization using multigrid-based technique, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
Li, Di-an, Marek-Sadowska, M., and Lee, B., On-chip em-sensitive interconnect structures, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
M. Marek-Sadowska, On old and new routing problems, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, pp. 13–20.
Y. - L. Wu, Fan, H., Marek-Sadowska, M., and Wong, C. K., OBDD minimization based on two-level representation of Boolean functions, Computers, IEEE Transactions on, vol. 49, pp. 1371 -1379, 2000.
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A. Singh, Macchiarulo, L., Mukherjee, A., and Marek-Sadowska, M., A novel high throughput reconfigurable FPGA architecture, in FPGA '00: Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, 2000, pp. 22–29.
Y. - L. Wu, Chang, D., Marek-Sadowska, M., and Tsukiyama, S., Not necessarily more switches more routability [sic.], in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., A new reasoning scheme for efficient redundancy addition and removal, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A new hybrid methodology for power estimation, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 439 -444.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., A New Accurate and Efficient Timing Simulator, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
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Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Multiple fault diagnosis using n-detection tests, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
C. - C. Tsai and Marek-Sadowska, M., Multilevel logic synthesis for arithmetic functions, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 242 -247.

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