Publications

Found 231 results
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L. H. Chen and Marek-Sadowska, M., Aggressor alignment for worst-case coupling noise, in ISPD '00: Proceedings of the 2000 international symposium on Physical design, 2000, pp. 48–54.
B. Chen and Marek-Sadowska, M., Timing driven placement of pads and latches, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
L. H. Chen and Marek-Sadowska, M., Closed-Form Crosstalk Noise Delay Metrics, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
L. H. Chen and Marek-Sadowska, M., Aggresors alignment for worst-case coupling noise, in ICCAD '00: Proceedings of the 2000 international conference on Computer-aided design, 2000, pp. 48–54.
L. H. Chen and Marek-Sadowska, M., Efficient closed-form crosstalk delay metrics, in Quality Electronic Design, 2002. Proceedings. International Symposium on, 2002, pp. 431 - 436.
L. H. Chen, Marek-Sadowska, M., Divecha, R., and Singh, P., Capturing input switching dependency in crosstalk noise modeling, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
D. Chang and Marek-Sadowska, M., Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
D. Chang, Lee, T. - C., Marek-Sadowska, M., Aikyo, T., and Cheng, K. - T., A Test Synthesis Approach To Reducing Ballast Dft Overhead, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Layout Driven Logic Synthesis for FPGAs, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., Minimizing ROBDD size of incompletely specified multiple output functions, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
C. - W. Chang and Marek-Sadowska, M., Theory of wire addition and removal in combinational Boolean networks, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
C. - W. Chang, Cheng, C. - K., Suaris, P., and Marek-Sadowska, M., Fast post-placement rewiring using easily detectable functional symmetries, in Design Automation Conference, 2000. Proceedings 2000. 37th, 2000, pp. 286 -289.
D. Chang and Marek-Sadowska, M., Partitioning sequential circuits on dynamically reconfigurable FPGAs, Computers, IEEE Transactions on, vol. 48, pp. 565 -578, 1999.
C. - W. Chang and Marek-Sadowska, M., Who are the alternative wires in your neighborhood? (alternative wires identification without search), in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.
S. - C. Chang and Marek-Sadowska, M., Technology mapping and circuit depth optimization for field programmable gate arrays, in Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993, 1993, pp. 3.5.1 -3.5.4.
S. - C. Chang and Marek-Sadowska, M., Perturb and simplify: optimizing circuits with external don't cares, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 402 -406.
S. - C. Chang and Marek-Sadowska, M., Technology mapping via transformations of function graphs, in Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings., IEEE 1992 International Conference on, 1992, pp. 159 -162.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., Postlayout logic restructuring using alternative wires, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
C. - W. Chang and Marek-Sadowska, M., ATPG-based logic synthesis: an overview, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
D. Chang, Lee, T. - C., Cheng, K. - T., and Marek-Sadowska, M., Functional scan chain testing, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
S. - C. Chang and Marek-Sadowska, M., Perturb And Simplify: Multi-level Boolean Network Optimizer, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 2 -5.
C. - W. Chang and Marek-Sadowska, M., Single-pass redundancy-addition-and-removal, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Fast Boolean optimization by rewiring, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
S. - C. Chang, Marek-Sadowska, M., and Cheng, K. - T., An efficient algorithm for local don't care sets calculation, in DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation Conference, 1995, pp. 663–667.

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