Publications

Found 14 results
Filters: Author is Janusz Rajski  [Clear All Filters]
2009
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
2008
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
2006
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Analysis and methodology for multiple-fault diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
V. Mehta, Wang, Z., Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis for nonrobust test”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -472.
V. Mehta, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology”, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
2005
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
2004
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
2003
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., “Multiple fault diagnosis using n-detection tests”, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
2000
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Star test: the theory and its applications”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
1999
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
1997
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., “Starbist Scan Autocorrelated Random Pattern Generation”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.