Publications

Found 228 results
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Conference Paper
C. - Y. Yeh and Marek-Sadowska, M., Timing-aware power noise reduction in layout, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 627 - 634.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., Transistor-level layout of high-density regular circuits, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
W. Maly, Singh, N., Chen, Z., Shen, N., Li, X., Pfitzner, A., Kasprowicz, D., Kuzmicz, W., Yi-Wei Lin, and Marek-Sadowska, M., Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
M. Marek-Sadowska, Two-Dimensional Router for Double Layer Layout, in Design Automation, 1985. 22nd Conference on, 1985, pp. 117 - 123.
C. - C. Lin, Marek-Sadowska, M., and Gatlin, D., Universal Logic Gate For Fpga Design, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
Li, Di-an and Marek-Sadowska, M., Variation-aware electromigration analysis of power/ground networks, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
D. I. Cheng and Marek-Sadowska, M., Verifying equivalence of functions with unknown input correspondence, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 81 -85.
X. Qiu, Marek-Sadowska, M., and Maly, W., Vertical Slit Field Effect Transistor in ultra-low power applications, in Quality Electronic Design (ISQED), 2012 13th International Symposium on, 2012, pp. 384 -390.
Y. Ran and Marek-Sadowska, M., Via-configurable routing architectures and fast design mappability estimation for regular fabrics, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 25 - 32.
A. Mukherjee, Marek-Sadowska, M., and Long, S. I., Wave pipelining YADDs-a feasibility study, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
L. Macchiarulo, Shu, S. - M., and Marek-Sadowska, M., Wave steered FSMs, in Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings, 2000, pp. 270 -276.
A. Mukherjee, Sudhakar, R., Marek-Sadowska, M., and Long, S. I., Wave steering in YADDs: a novel non-iterative synthesis and layout technique, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
L. Macchiarulo and Marek-Sadowska, M., Wave-steering one-hot encoded FSMs, in DAC '00: Proceedings of the 37th Annual Design Automation Conference, 2000, pp. 357–360.
C. - W. Chang and Marek-Sadowska, M., Who are the alternative wires in your neighborhood? (alternative wires identification without search), in GLSVLSI '01: Proceedings of the 11th Great Lakes symposium on VLSI, 2001, pp. 103–108.
B. Hu and Marek-Sadowska, M., Wire length prediction based clustering and its application in placement, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
Q. Liu, Hu, B., and Marek-Sadowska, M., Wire length prediction in constraint driven placement, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
Q. Liu and Marek-Sadowska, M., Wire length prediction-based technology mapping and fanout optimization, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 145–151.
T. Xiao and Marek-Sadowska, M., Worst delay estimation in crosstalk aware static timing analysis, in Computer Design, 2000. Proceedings. 2000 International Conference on, 2000, pp. 115 -120.
Journal Article
L. H. Chen and Marek-Sadowska, M., Aggressor alignment for worst-case crosstalk noise, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, pp. 612 -621, 2001.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Analysis and methodology for multiple-fault diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
C. - C. Tsai and Marek-Sadowska, M., Boolean functions classification via fixed polarity Reed-Muller forms, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., Buffer delay change in the presence of power and ground noise, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
S. - C. Chang, Van Ginneken, L. P. P. P., and Marek-Sadowska, M., Circuit optimization by rewiring, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
A. Mukherjee and Marek-Sadowska, M., Clock and power gating with timing closure, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.

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