Publications
, “STAR-ATPG: a high speed test pattern generator for large scan designs”, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
, “Wave pipelining YADDs-a feasibility study”, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
, “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
, “Functional scan chain testing”, in Design, Automation and Test in Europe, 1998., Proceedings, 1998, pp. 278 -283.
, “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
, “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
, “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
, “Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs”, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
, “Crosstalk reduction for VLSI”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
, “Cube diagram bundles: a new representation of strongly unspecified multiple-valued functions and relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 287 -292.
, “Decomposition of multiple-valued relations”, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “Low-power buffered clock tree design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
, “Not necessarily more switches more routability [sic.]”, in Design Automation Conference 1997. Proceedings of the ASP-DAC '97. Asia and South Pacific, 1997, pp. 579 -584.
, “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
, “Postlayout logic restructuring using alternative wires”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 587 -596, 1997.
, “Routing for array-type FPGA's”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 506 -518, 1997.
, “Scan encoded test pattern generation for BIST”, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
, “Starbist Scan Autocorrelated Random Pattern Generation”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
, “A Test Synthesis Approach To Reducing Ballast Dft Overhead”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 466 -471.
, “Clock skew optimization for ground bounce control”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
, “Fast Boolean optimization by rewiring”, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 262 -269.
, “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
, “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
