Publications

Found 228 results
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Y. Ran and Marek-Sadowska, M., “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
G. Parthasarathy, Marek-Sadowska, M., Mukherjee, A., and Singh, A., “Interconnect complexity-aware FPGA placement using Rent's rule”, in SLIP '01: Proceedings of the 2001 international workshop on System-level interconnect prediction, 2001, pp. 115–121.
C. - K. Tsai and Marek-Sadowska, M., “An interconnect insensitive linear time-varying driver model for static timing analysis”, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Interconnect pipelining in a throughput-intensive FPGA architecture”, in FPGA '01: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, 2001, pp. 153–160.
A. Singh, Parthasarathy, G., and Marek-Sadowska, M., “Interconnect resource-aware placement for hierarchical FPGAs”, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 132 -136.
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A. Singh, Mukherjee, A., and Marek-Sadowska, M., “Latency and latch count minimization in wave steered circuits”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 383 - 388.
S. - C. Chang, Cheng, K. - T., Woo, N. - S., and Marek-Sadowska, M., “Layout Driven Logic Synthesis for FPGAs”, in Design Automation, 1994. 31st Conference on, 1994, pp. 308 - 313.
V. S. Nandakumar and Marek-Sadowska, M., “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
C. - W. Chang, Wang, K., and Marek-Sadowska, M., “Layout-driven hot-carrier degradation minimization using logic restructuring techniques”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 97 - 102.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Tsai and Marek-Sadowska, M., “Logic synthesis for testability”, in VLSI, 1996. Proceedings., Sixth Great Lakes Symposium on, 1996, pp. 118 -121.
V. S. Nandakumar and Marek-Sadowska, M., “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
A. Vittal and Marek-Sadowska, M., “Low-power buffered clock tree design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
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Y. Ran and Marek-Sadowska, M., “The magic of a via-configurable regular fabric”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., “Metrics for characterizing machine learning-based hotspot detection methods”, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, pp. 1 -6.
B. Hu, Zeng, Y., and Marek-Sadowska, M., “mFAR: fixed-points-addition-based VLSI placement algorithm”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
A. Vittal and Marek-Sadowska, M., “Minimal Delay Interconnect Design Using Alphabetic Trees”, in Design Automation, 1994. 31st Conference on, 1994, pp. 392 - 396.
C. - C. Tsai and Marek-Sadowska, M., “Minimisation of fixed-polarity AND/XOR canonical networks”, Computers and Digital Techniques, IEE Proceedings -, vol. 141, pp. 369 -374, 1994.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
S. - C. Chang, Cheng, D. I., and Marek-Sadowska, M., “Minimizing ROBDD size of incompletely specified multiple output functions”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 620 -624.
C. - Y. Yeh and Marek-Sadowska, M., “Minimum-area sequential budgeting for FPGA”, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., “Modeling crosstalk in resistive VLSI interconnections”, in VLSI Design, 1999. Proceedings. Twelfth International Conference On, 1999, pp. 470 -475.

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