Publications

Found 231 results
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C. - C. Lin, Lee, T. - C., Marek-Sadowska, M., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., “Sequential permissible functions and their application to circuit optimization”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
Li, Di-an, Marek-Sadowska, M., and Lee, B., “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
J. - T. Li and Marek-Sadowska, M., “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
Li, Di-an and Marek-Sadowska, M., “Variation-aware electromigration analysis of power/ground networks”, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
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Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
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Y. - M. Jiang, Krstic, A., Cheng, K. - T., and Marek-Sadowska, M., “Post-layout Logic Restructuring For Performance Optimization”, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 662 -665.
H. Jiang, Wang, K., and Marek-Sadowska, M., “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
H. Jiang, Marek-Sadowska, M., and Nassif, S. R., “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
H. Jiang and Marek-Sadowska, M., “Power gating scheduling for power/ground noise reduction”, in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, 2008, pp. 980 -985.
H. Jiang and Marek-Sadowska, M., “Power/Ground Supply Network Optimization for Power-Gating”, in Computer Design, 2006. ICCD 2006. International Conference on, 2006, pp. 332 -337.
H. Jiang and Marek-Sadowska, M., “Power-Gating Aware Floorplanning”, in Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, 2007, pp. 853 -860.
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B. Hu and Marek-Sadowska, M., “FAR: fixed-points addition & relaxation based placement”, in ISPD '02: Proceedings of the 2002 international symposium on Physical design, 2002, pp. 161–166.
B. Hu and Marek-Sadowska, M., “Multilevel fixed-point-addition-based VLSI placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
B. Hu and Marek-Sadowska, M., “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.

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