Publications

Found 33 results
Filters: First Letter Of Last Name is L  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
L
Li, Di-an and Marek-Sadowska, M., “Variation-aware electromigration analysis of power/ground networks”, in Computer-Aided Design (ICCAD), 2011 IEEE/ACM International Conference on, 2011, pp. 571 -576.
Li, Di-an, Marek-Sadowska, M., and Lee, B., “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
J. - T. Li and Marek-Sadowska, M., “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “A New Accurate and Efficient Timing Simulator”, in VLSI Design, 1992. Proceedings., The Fifth International Conference on, 1992, pp. 281 -286.
C. - C. Lin, Chang, D., Wu, Y. - L., and Marek-Sadowska, M., “Time-multiplexed routing resources for FPGA design”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 152 -155.
S. Lin and Marek-Sadowska, M., “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
C. - C. Lin, Marek-Sadowska, M., Lee, T. - C., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., “Stepwise equivalent conductance circuit simulation technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Transistor-level layout of high-density regular circuits”, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., “Sequential permissible functions and their application to circuit optimization”, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Test-point insertion: scan paths through functional logic”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 838 -851, 1998.
C. - C. Lin, Marek-Sadowska, M., and Gatlin, D., “Universal Logic Gate For Fpga Design”, in Computer-Aided Design, 1994., IEEE/ACM International Conference on, 1994, pp. 164 -168.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Test point insertion: scan paths through combinational logic”, in Design Automation Conference Proceedings 1996, 33rd, 1996, pp. 268 -273.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
Yi-Wei Lin, Marek-Sadowska, M., and Maly, W., “On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
C. - C. Lin, Lee, T. - C., Marek-Sadowska, M., and Chen, K. - C., “Cost-free scan: a low-overhead scan path design methodology”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 528 -533.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., “Scan paths through functional logic”, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
S. Lin and Marek-Sadowska, M., “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
C. - C. Lin, Chen, K. - C., Cheng, D. I., and Marek-Sadowska, M., “Logic rectification and synthesis for engineering change”, in Design Automation Conference, 1995. Proceedings of the ASP-DAC '95/CHDL '95/VLSI '95., IFIP International Conference on Hardware Description Languages; IFIP International Conference on Very Large Scale Integration., Asian and South Pacific, 1995, pp. 301 -309.
Yi-Wei Lin, Marek-Sadowska, M., Maly, W., Pfitzner, A., and Kasprowicz, D., “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
C. - C. Lin and Marek-Sadowska, M., “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.

Pages