Publications
Found 228 results
Filters: Author is Malgorzata Marek-Sadowska [Clear All Filters]
, “An accurate and efficient delay model for CMOS gates in switch-level timing analysis”, in Circuits and Systems, 1990., IEEE International Symposium on, 1990, pp. 856 -860 vol.2.
, “Aggresors alignment for worst-case coupling noise”, in ICCAD '00: Proceedings of the 2000 international conference on Computer-aided design, 2000, pp. 48–54.
, “Aggressor alignment for worst-case coupling noise”, in ISPD '00: Proceedings of the 2000 international symposium on Physical design, 2000, pp. 48–54.
, “Aggressor alignment for worst-case crosstalk noise”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 20, pp. 612 -621, 2001.
, “Analysis and methodology for multiple-fault diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
, “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
, “Analysis of Heuristic Reasoning for the Visualization of CAD Quadratic”, in ICCAL '89: Proceedings of the 2nd International Conference on Computer Assisted Learning, 1989, pp. 359–378.
, “Analysis of process variation's effect on SRAM's read stability”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -610.
, “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
, “Automatic Sizing of Power/Ground (P/G) Networks in VLSI”, in Design Automation, 1989. 26th Conference on, 1989, pp. 783 - 786.
, “Benefits and costs of power-gating technique”, in 2005 IEEE International Conference on Computer Design , 2005, pp. 559 - 566.
, “Boolean functions classification via fixed polarity Reed-Muller forms”, Computers, IEEE Transactions on, vol. 46, pp. 173 -186, 1997.
, “Boolean Matching Using Generalized Reed-Muller Forms”, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
, “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
, “Buffer minimization and time-multiplexed I/O on dynamically reconfigurable FPGAs”, in FPGA '97: Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, 1997, pp. 142–148.
, “Buffer sizing for clock power minimization subject to general skew constraints”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
, “Can pin access limit the footprint scaling?”, in Proceedings of the 49th Annual Design Automation Conference, 2012, pp. 1100–1106.
, “Capturing input switching dependency in crosstalk noise modeling”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
, “On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
, “Circuit clustering using graph coloring”, in ISPD '99: Proceedings of the 1999 international symposium on Physical design, 1999, pp. 164–169.
, “Circuit optimization by rewiring”, Computers, IEEE Transactions on, vol. 48, pp. 962 -970, 1999.
, “Circuit partitioning with logic perturbation”, in Computer-Aided Design, 1995. ICCAD-95. Digest of Technical Papers., 1995 IEEE/ACM International Conference on, 1995, pp. 650 -655.
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
, “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
