Publications

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C. - W. Chang and Marek-Sadowska, M., Single-pass redundancy-addition-and-removal, in Computer Aided Design, 2001. ICCAD 2001. IEEE/ACM International Conference on, 2001, pp. 606 -609.
D. I. Cheng, Marek-Sadowska, M., and Cheng, K. - T., Speeding up power estimation by topological analysis, in Custom Integrated Circuits Conference, 1995., Proceedings of the IEEE 1995, 1995, pp. 623 -626.
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B. Hu, Jiang, H., Liu, Q., and Marek-Sadowska, M., Synthesis and placement flow for gain-based programmable regular fabrics, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
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Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., Spare Cells With Constant Insertion for Engineering Change, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
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C. - C. Lin, Chen, K. - C., Marek-Sadowska, M., and Lee, T. - C., Sequential permissible functions and their application to circuit optimization, in European Design and Test Conference, 1996. ED TC 96. Proceedings, 1996, pp. 334 -339.
C. - C. Lin, Marek-Sadowska, M., Cheng, K. - T., and Lee, T. - C., Scan paths through functional logic, in Custom Integrated Circuits Conference, 1996., Proceedings of the IEEE 1996, 1996, pp. 487 -490.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
S. Lin, Kuh, E. S., and Marek-Sadowska, M., Stepwise equivalent conductance circuit simulation technique, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 12, pp. 672 -683, 1993.
Q. Liu and Marek-Sadowska, M., A study of netlist structure and placement efficiency, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.
Q. Liu and Marek-Sadowska, M., Semi-individual wire-length prediction with application to logic synthesis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 611 - 624, 2006.
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M. Marek-Sadowska and Tarng, T. T. - K., Single-Layer Routing for VLSI: Analysis and Algorithms, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.
M. Marek-Sadowska and Qiu, X., A study on cell-level routing for VeSFET circuits, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.
M. Marek-Sadowska, Switch box routing: a retrospective, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
A. Mukherjee, Wang, K., Chen, L. H., and Marek-Sadowska, M., Sizing power/ground meshes for clocking and computing circuit components, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
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V. S. Nandakumar, Newmark, D., Zhan, Y., and Marek-Sadowska, M., Statistical static timing analysis flow for transistor level macros in a microprocessor, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
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A. Todri and Marek-Sadowska, M., A study of reliability issues in clock distribution networks, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
A. Todri, Marek-Sadowska, M., Maire, F., and Matheron, C., A study of decoupling capacitor effectiveness in power and ground grid networks, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Star test: the theory and its applications, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Scan encoded test pattern generation for BIST, in Test Conference, 1997. Proceedings., International, 1997, pp. 548 -556.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., Starbist Scan Autocorrelated Random Pattern Generation, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., STAR-ATPG: a high speed test pattern generator for large scan designs, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
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C. - Y. Yeh and Marek-Sadowska, M., Sequential delay budgeting with interconnect prediction, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
C. - Y. Yeh and Marek-Sadowska, M., Skew-programmable clock design for FPGA and skew-aware placement, in FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005, pp. 33–40.