Publications

Found 231 results
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C. - C. Tsai and Marek-Sadowska, M., Detecting symmetric variables in Boolean functions using generalized Reed-Muller forms, in Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on, 1994, vol. 1, pp. 287 -290 vol.1.
K. - H. Tsai, Hellebrand, S., Rajski, J., and Marek-Sadowska, M., Starbist Scan Autocorrelated Random Pattern Generation, in Design Automation Conference, 1997. Proceedings of the 34th, 1997, pp. 472 -477.
C. - C. Tsai and Marek-Sadowska, M., Generalized Reed-Muller forms as a tool to detect symmetries, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
C. - K. Tsai and Marek-Sadowska, M., Modeling crosstalk induced delay, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
K. - H. Tsai, Rajski, J., and Marek-Sadowska, M., Star test: the theory and its applications, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 19, pp. 1052 -1064, 2000.
C. - C. Tsai and Marek-Sadowska, M., Boolean Matching Using Generalized Reed-Muller Forms, in Design Automation, 1994. 31st Conference on, 1994, pp. 339 - 344.
K. - H. Tsai, Tompson, R., Rajski, J., and Marek-Sadowska, M., STAR-ATPG: a high speed test pattern generator for large scan designs, in Test Conference, 1999. Proceedings. International, 1999, pp. 1021 -1030.
C. - C. Tsai and Marek-Sadowska, M., Efficient minimization algorithms for fixed polarity AND/XOR canonical networks, in VLSI, 1993. 'Design Automation of High Performance VLSI Systems', Proceedings., Third Great Lakes Symposium on, 1993, pp. 76 -79.
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A. Vittal and Marek-Sadowska, M., Minimal Delay Interconnect Design Using Alphabetic Trees, in Design Automation, 1994. 31st Conference on, 1994, pp. 392 - 396.
A. Vittal and Marek-Sadowska, M., Low-power buffered clock tree design, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 965 -975, 1997.
A. Vittal and Marek-Sadowska, M., Power Optimal Buffered Clock Tree Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 497 -502.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Modeling crosstalk in resistive VLSI interconnections, in VLSI Design, 1999. Proceedings. Twelfth International Conference On, 1999, pp. 470 -475.
A. Vittal, Ha, H., Brewer, F., and Marek-Sadowska, M., Clock skew optimization for ground bounce control, in Computer-Aided Design, 1996. ICCAD-96. Digest of Technical Papers., 1996 IEEE/ACM International Conference on, 1996, pp. 395 -399.
A. Vittal and Marek-Sadowska, M., Crosstalk reduction for VLSI, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
A. Vittal and Marek-Sadowska, M., Power Distribution Topology Design, in Design Automation, 1995. DAC '95. 32nd Conference on, 1995, pp. 503 -507.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Crosstalk in VLSI interconnections, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
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K. Wang and Marek-Sadowska, M., Potential slack budgeting with clock skew optimization, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
K. Wang and Marek-Sadowska, M., On-chip power supply network optimization using multigrid-based technique, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Multiple fault diagnosis using n-detection tests, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay fault diagnosis using timing information, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay-fault diagnosis using timing information, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
K. Wang and Marek-Sadowska, M., Power/ground mesh area optimization using multigrid-based technique [IC design], in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
K. Wang and Marek-Sadowska, M., Buffer sizing for clock power minimization subject to general skew constraints, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.

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