Publications

Found 85 results
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2012
F. Chen, Mittl, S., Shinosky, M., Swift, A., Kontra, R., Anderson, B., Aitken, J., Wang, Y., Kinser, E., Kumar, M., Wang, Y., Kane, T., Feng, K. D., Henson, W. K., Mocuta, D., and Li, Di-an, “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
2011
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
W. Maly, Singh, N., Chen, Z., Shen, N., Li, X., Pfitzner, A., Kasprowicz, D., Kuzmicz, W., Yi-Wei Lin, and Marek-Sadowska, M., “Twin gate, vertical slit FET (VeSFET) for highly periodic layout and 3D integration”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 145 -150.
2009
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
2008
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
2007
A. Todri, Marek-Sadowska, M., and Chang, S. - C., “Analysis and optimization of power-gated ICs with multiple power gating configurations”, in Computer-Aided Design, 2007. ICCAD 2007. IEEE/ACM International Conference on, 2007, pp. 783 -790.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., “An Efficient Mechanism for Performance Optimization of Variable-Latency Designs”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
A. Todri, Chang, S. - C., and Marek-Sadowska, M., “Electromigration and voltage drop aware power grid optimization for power gated ICs”, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on, 2007, pp. 391 -394.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
Y. - M. Kuo, Chang, Y. - T., Chang, S. - C., and Marek-Sadowska, M., “Engineering change using spare cells with constant insertion”, in ICCAD '07: Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design, 2007, pp. 544–547.
C. - W. Chang and Marek-Sadowska, M., “Theory of wire addition and removal in combinational Boolean networks”, Microelectron. Eng., vol. 84, pp. 229–243, 2007.
2004
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
2003
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
L. H. Chen and Marek-Sadowska, M., “Closed-Form Crosstalk Noise Delay Metrics”, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
C. - W. Chang, Hsiao, M. - F., and Marek-Sadowska, M., “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
D. Chai, Kondratyev, A., Ran, Y., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
2002
C. - W. Chang and Marek-Sadowska, M., “ATPG-based logic synthesis: an overview”, in Computer Aided Design, 2002. ICCAD 2002. IEEE/ACM International Conference on, 2002, pp. 786 - 789.
L. H. Chen and Marek-Sadowska, M., “Closed-form crosstalk noise metrics for physical design applications”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 812 - 819.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Coping with buffer delay change due to power and ground noise”, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.

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