Publications
Found 228 results
Filters: Author is Malgorzata Marek-Sadowska [Clear All Filters]
, “Clock skew bounds estimation under power supply and process variations”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
, “A congestion-driven placement framework with local congestion prediction”, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 488–493.
, “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
, “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
, “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
, “An interconnect insensitive linear time-varying driver model for static timing analysis”, in Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on, 2005, pp. 654 - 661.
, “mFAR: fixed-points-addition-based VLSI placement algorithm”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 239–241.
, “Multilevel fixed-point-addition-based VLSI placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1188 - 1203, 2005.
, “On-chip power-supply network optimization using multigrid-based technique”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 407 - 417, 2005.
, “Pre-layout physical connectivity prediction with application in clustering-based placement”, in Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005. Proceedings. 2005 IEEE International Conference on, 2005, pp. 31 - 37.
, “Skew-programmable clock design for FPGA and skew-aware placement”, in FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005, pp. 33–40.
, “A study of netlist structure and placement efficiency”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 762 - 772, 2005.
, “Timing-aware power noise reduction in layout”, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 627 - 634.
, “Via-configurable routing architectures and fast design mappability estimation for regular fabrics”, in Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on, 2005, pp. 25 - 32.
, “Wire length prediction-based technology mapping and fanout optimization”, in ISPD '05: Proceedings of the 2005 international symposium on Physical design, 2005, pp. 145–151.
, “Buffer sizing for clock power minimization subject to general skew constraints”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
, “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
, “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
, “Designing a via-configurable regular fabric”, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.
, “On designing via-configurable cell blocks for regular fabrics”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 198 -203.
, “Diagnosis of hold time defects”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
, “Eliminating false positives in crosstalk noise analysis”, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
, “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
