Publications

Found 50 results
Filters: First Letter Of Last Name is W  [Clear All Filters]
A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 
A
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Analysis and methodology for multiple-fault diagnosis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 25, pp. 558 - 575, 2006.
B
K. Wang and Marek-Sadowska, M., Buffer sizing for clock power minimization subject to general skew constraints, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
C
K. Wang and Marek-Sadowska, M., Clock network sizing via sequential linear programming with time-domain analysis, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
H. Jiang, Wang, K., and Marek-Sadowska, M., Clock skew bounds estimation under power supply and process variations, in GLSVLSI '05: Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005, pp. 332–336.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., On computational complexity of a detailed routing problem in two dimensional FPGAs, in VLSI, 1994. Design Automation of High Performance VLSI Systems. GLSV '94, Proceedings., Fourth Great Lakes Symposium on, 1994, pp. 70 -75.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., Crosstalk in VLSI interconnections, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
D
M. Perkowski, Marek-Sadowska, M., Jozwiak, L., Luba, T., Grygiel, S., Nowicka, M., Malvi, R., Wang, Z., and Zhang, J. S., Decomposition of multiple-valued relations, in Multiple-Valued Logic, 1997. Proceedings., 1997 27th International Symposium on, 1997, pp. 13 -18.
V. Mehta, Wang, Z., Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay fault diagnosis for nonrobust test, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -472.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay fault diagnosis using timing information, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Delay-fault diagnosis using timing information, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
J. - Y. Wuu, Pikus, F. G., Torres, A., Marek-Sadowska, M., Singh, V. K., and Rieger, M. L., Detecting context sensitive hot spots in standard cell libraries, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
Z. Wang, Marek-Sadowska, M., Tsai, K. - H., and Rajski, J., Diagnosis of hold time defects, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 192 - 199.
E
J. - Y. Wuu, Pikus, F. G., Marek-Sadowska, M., and Rieger, M. L., Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
Y. - S. Su, Wang, D. - C., Chang, S. - C., and Marek-Sadowska, M., An Efficient Mechanism for Performance Optimization of Variable-Latency Designs, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 976 -981.
Y. - L. Wu and Marek-Sadowska, M., Efficient ordered binary decision diagrams minimization based on heuristics of cover pattern processing, in Design Automation, 1993, with the European Event in ASIC Design. Proceedings. [4th] European Conference on, 1993, pp. 273 -277.
Y. - L. Wu and Marek-Sadowska, M., An efficient router for 2-D field programmable gate array, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
Y. Ran, Kondratyev, A., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
Y. Ran, Kondratyev, A., Watanabe, Y., and Marek-Sadowska, M., Eliminating false positives in crosstalk noise analysis, in Design, Automation and Test in Europe Conference and Exhibition, 2004. Proceedings, 2004, vol. 2, pp. 1192 - 1197 Vol.2.
F
J. - Y. Wuu, Pikus, F. G., and Marek-Sadowska, M., Fast and simple modeling of non-rectangular transistors, in Society of Photo-Optical Instrumentation Engineers (SPIE) Conference Series, 2008, vol. 7122.
C. - W. Chang, Hsiao, M. - F., Hu, B., Wang, K., Marek-Sadowska, M., Cheng, C. - K., and Chen, S. - J., Fast postplacement optimization using functional symmetries, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
G
B. Hu, Watanabe, Y., and Marek-Sadowska, M., Gain-based technology mapping for discrete-size cell libraries, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
K. Wang, Ran, Y., Jiang, H., and Marek-Sadowska, M., General skew constrained clock network sizing based on sequential linear programming, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
Y. - L. Wu, Tsukiyama, S., and Marek-Sadowska, M., Graph based analysis of 2-D FPGA routing, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
Y. - L. Wu and Marek-Sadowska, M., Graph based analysis of FPGA routing, in Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93. European, 1993, pp. 104 -109.
H
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., A hybrid methodology for switching activities estimation, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.

Pages