Publications
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
, “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
, “An integrated design flow for a via-configurable gate array”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 582 - 589.
, “The magic of a via-configurable regular fabric”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 338 - 343.
, “Multilevel expansion-based VLSI placement with blockages”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
, “Pipelining sequential circuits with wave steering”, Computers, IEEE Transactions on, vol. 53, pp. 1205 - 1210, 2004.
, “Potential slack budgeting with clock skew optimization”, in Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings. IEEE International Conference on, 2004, pp. 265 - 271.
, “Pre-layout wire length and congestion estimation”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 582 -587.
, “Sequential delay budgeting with interconnect prediction”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1028 -1037, 2004.
, “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Closed-Form Crosstalk Noise Delay Metrics”, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
, “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
, “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
, “Delay budgeting in sequential circuit with application on FPGA placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
, “Fine granularity clustering for large scale placement problems”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
, “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
, “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
, “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
, “Minimum-area sequential budgeting for FPGA”, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.
, “Modeling crosstalk induced delay”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
, “Multiple fault diagnosis using n-detection tests”, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
, “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
, “On-chip power supply network optimization using multigrid-based technique”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
