- Vertical Slit Field Effect Transistor in ultra-low power applications
- Can pin access limit the footprint scaling?
- A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures
- Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues
- Metrics for characterizing machine learning-based hotspot detection methods
- A study on cell-level routing for VeSFET circuits
- On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits
Publications
, “A study of reliability issues in clock distribution networks”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 101 -106.
, “Is there always performance overhead for regular fabric?”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 557 -562.
, “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
, “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
, “Detecting context sensitive hot spots in standard cell libraries”, in Design for Manufacturability through Design-Process Integration III, 2009, vol. 7275, p. 727515.
, “Electromigration study of power-gated grids”, in ISLPED '09: Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design, 2009, pp. 315–318.
, “Spare Cells With Constant Insertion for Engineering Change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 456 -460, 2009.
, “A study of decoupling capacitor effectiveness in power and ground grid networks”, in Quality of Electronic Design, 2009. ISQED 2009. Quality Electronic Design, 2009, pp. 653 -658.
, “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
, “Transistor-level layout of high-density regular circuits”, in ISPD '09: Proceedings of the 2009 international symposium on Physical design, 2009, pp. 83–90.
, “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
, “On-chip em-sensitive interconnect structures”, in SLIP '10: Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction, 2010, pp. 43–50.
, “Performance study of VeSFET-based, high-density regular circuits”, in ISPD '10: Proceedings of the 19th international symposium on Physical design, 2010, pp. 161–168.
, “Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
, “On Cell Layout-Performance Relationships in VeSFET-Based, High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp. 229 -241, 2011.
, “Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching”, in Design for Manufacturability through Design-Process Integration V, 2011, vol. 7974.
, “Layout effects in fine grain 3D integrated regular microprocessor blocks”, in Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, 2011, pp. 639 -644.
, “Low power, high throughput network-on-chip fabric for 3D multicore processors”, in Computer Design (ICCD), 2011 IEEE 29th International Conference on, 2011, pp. 453 -454.
, “Metrics for characterizing machine learning-based hotspot detection methods”, in Quality Electronic Design (ISQED), 2011 12th International Symposium on, 2011, pp. 1 -6.
, “On old and new routing problems”, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, pp. 13–20.
, “Performance Optimization Using Variable-Latency Design Style”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 1874 -1883, 2011.
, “Power Delivery for Multicore Systems”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 2243 -2255, 2011.
, “Rapid layout pattern classification”, in Design Automation Conference (ASP-DAC), 2011 16th Asia and South Pacific, 2011, pp. 781 -786.
, “Reliability Analysis and Optimization of Power-Gated ICs”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19, pp. 457 -468, 2011.
, “A study on cell-level routing for VeSFET circuits”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.
