Publications
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Closed-Form Crosstalk Noise Delay Metrics”, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
, “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
, “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
, “Delay budgeting in sequential circuit with application on FPGA placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 202 - 207.
, “Fine granularity clustering for large scale placement problems”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 67–74.
, “Gain-based technology mapping for discrete-size cell libraries”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 574 - 579.
, “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
, “Minimizing inter-clock coupling jitter”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 333 - 338.
, “Minimum-area sequential budgeting for FPGA”, in Computer Aided Design, 2003. ICCAD-2003. International Conference on, 2003, pp. 813 - 817.
, “Modeling crosstalk induced delay”, in Quality Electronic Design, 2003. Proceedings. Fourth International Symposium on, 2003, pp. 189 - 194.
, “Multiple fault diagnosis using n-detection tests”, in Computer Design, 2003. Proceedings. 21st International Conference on, 2003, pp. 198 - 201.
, “A new reasoning scheme for efficient redundancy addition and removal”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 22, pp. 945 - 951, 2003.
, “On-chip power supply network optimization using multigrid-based technique”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 113 - 118.
, “PITIA: an FPGA for throughput-intensive applications”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 354 -363, 2003.
, “Power/ground mesh area optimization using multigrid-based technique [IC design]”, in Design, Automation and Test in Europe Conference and Exhibition, 2003, 2003, pp. 850 - 855.
, “Synthesis and placement flow for gain-based programmable regular fabrics”, in ISPD '03: Proceedings of the 2003 international symposium on Physical design, 2003, pp. 197–203.
, “Temporofunctional crosstalk noise analysis”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 860 - 863.
, “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
, “Wire length prediction based clustering and its application in placement”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 800 - 805.
, “Wire length prediction in constraint driven placement”, in SLIP '03: Proceedings of the 2003 international workshop on System-level interconnect prediction, 2003, pp. 99–105.
, “Buffer sizing for clock power minimization subject to general skew constraints”, in Design Automation Conference, 2004. Proceedings. 41st, 2004, pp. 159 -164.
, “Clock network sizing via sequential linear programming with time-domain analysis”, in ISPD '04: Proceedings of the 2004 international symposium on Physical design, 2004, pp. 182–189.
, “Delay fault diagnosis using timing information”, in Quality Electronic Design, 2004. Proceedings. 5th International Symposium on, 2004, pp. 485 - 490.
, “Designing a via-configurable regular fabric”, in Custom Integrated Circuits Conference, 2004. Proceedings of the IEEE 2004, 2004, pp. 423 - 426.
