Publications
“Statistical static timing analysis flow for transistor level macros in a microprocessor”, in Quality Electronic Design (ISQED), 2010 11th International Symposium on, 2010, pp. 163 -170.
, “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
, “Wave pipelining YADDs-a feasibility study”, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
, “Wave steering to integrate logic and physical syntheses”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 105 -120, 2003.
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Wave steering in YADDs: a novel non-iterative synthesis and layout technique”, in Design Automation Conference, 1999. Proceedings. 36th, 1999, pp. 466 -471.
, “Sizing power/ground meshes for clocking and computing circuit components”, in Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings, 2002, pp. 176 -183.
, “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
, “Timing-Aware Multiple-Delay-Fault Diagnosis”, in Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on, 2008, pp. 246 -253.
, “Timing-Aware Multiple-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 28, pp. 245 -258, 2009.
, “Delay fault diagnosis for nonrobust test”, in Quality Electronic Design, 2006. ISQED '06. 7th International Symposium on, 2006, p. 8 pp. -472.
, “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
, “Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology”, in Test Conference, 2006. ITC '06. IEEE International, 2006, pp. 1-10.
, “General channel-routing algorithm”, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
, “Pad Assignment for Power Nets in VLSI Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 6, pp. 550 - 560, 1987.
, “An Unconstrained Topological Via Minimization Problem for Two-Layer Routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 184 - 190, 1984.
, “Pin assignment for improved performance in standard cell design”, in Computer Design: VLSI in Computers and Processors, 1990. ICCD '90. Proceedings., 1990 IEEE International Conference on, 1990, pp. 339 -342.
, “Timing driven placement”, in Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on, 1989, pp. 94 -97.
, “On old and new routing problems”, in ISPD '11: Proceedings of the 2011 international symposium on Physical design, 2011, pp. 13–20.
, “Switch box routing: a retrospective”, Integr. VLSI J., vol. 13, pp. 39–65, 1992.
, “The crossing distribution problem [IC layout]”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 14, pp. 423 -433, 1995.
, “Single-Layer Routing for VLSI: Analysis and Algorithms”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 2, pp. 246 - 259, 1983.
, “The crossing distribution problem”, in Computer-Aided Design, 1991. ICCAD-91. Digest of Technical Papers., 1991 IEEE International Conference on, 1991, pp. 528 -531.
, “Two-Dimensional Router for Double Layer Layout”, in Design Automation, 1985. 22nd Conference on, 1985, pp. 117 - 123.
, “A study on cell-level routing for VeSFET circuits”, in Mixed Design of Integrated Circuits and Systems (MIXDES), 2011 Proceedings of the 18th International Conference, 2011, pp. 127 -132.
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