Publications
, “Clock and power gating with timing closure”, Design Test of Computers, IEEE, vol. 20, pp. 32 - 39, 2003.
, “Closed-Form Crosstalk Noise Delay Metrics”, Analog Integr. Circuits Signal Process., vol. 35, pp. 143–156, 2003.
, “Cost-free scan: a low-overhead scan path design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 852 -861, 1998.
, “The crossing distribution problem [IC layout]”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 14, pp. 423 -433, 1995.
, “Crosstalk in VLSI interconnections”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
, “Crosstalk reduction for VLSI”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
, “Delay-fault diagnosis using timing information”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1315 - 1325, 2005.
, “On designing universal logic blocks and their application to FPGA design”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 519 -527, 1997.
, “Designing via-configurable logic blocks for regular fabric”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 14, pp. 1 -14, 2006.
, “Efficient circuit clustering for area and power reduction in FPGAs”, ACM Trans. Des. Autom. Electron. Syst., vol. 7, pp. 643–663, 2002.
, “An Efficient Single-Row Routing Algorithm”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 178 - 183, 1984.
, “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
, “Fast postplacement optimization using functional symmetries”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 102 - 118, 2004.
, “Fine granularity clustering-based placement”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 23, pp. 527 - 536, 2004.
, “General channel-routing algorithm”, Electronic Circuits and Systems, IEE Proceedings G, vol. 130, pp. 83 -88, 1983.
, “General skew constrained clock network sizing based on sequential linear programming”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 773 - 782, 2005.
, “Generalized Reed-Muller forms as a tool to detect symmetries”, Computers, IEEE Transactions on, vol. 45, pp. 33 -40, 1996.
, “Global Routing for Gate Array”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 3, pp. 298 - 307, 1984.
, “Graph based analysis of 2-D FPGA routing”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 15, pp. 33 -44, 1996.
, “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
, “Improving the Resolution of Single-Delay-Fault Diagnosis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 27, pp. 932 -945, 2008.
, “Individual wire-length prediction with application to timing-driven placement”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 12, pp. 1004 -1014, 2004.
, “Layout Generator for Transistor-Level High-Density Regular Circuits”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 29, pp. 197 -210, 2010.
, “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.
, “A Low Energy Network-on-Chip Fabric for 3-D Multi-Core Architectures”, Emerging and Selected Topics in Circuits and Systems, IEEE Journal on, vol. 2, pp. 266 -277, 2012.
