Publications

Found 28 results
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Conference Paper
L. H. Chen, Marek-Sadowska, M., Divecha, R., and Singh, P., “Capturing input switching dependency in crosstalk noise modeling”, in ASIC/SOC Conference, 2000. Proceedings. 13th Annual IEEE International, 2000, pp. 330 -334.
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Coping with buffer delay change due to power and ground noise”, in Design Automation Conference, 2002. Proceedings. 39th, 2002, pp. 860 - 865.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “A crosstalk aware two-pin net router”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-485 - V-488 vol.5.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Crosstalk minimization for multiple clock tree routing”, in Circuits and Systems, 2002. MWSCAS-2002. The 2002 45th Midwest Symposium on, 2002, vol. 1, pp. I - 152-5 vol.1.
Y. Ran and Marek-Sadowska, M., “Crosstalk noise in FPGAs”, in Design Automation Conference, 2003. Proceedings, 2003, pp. 944 - 949.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “Delay and area optimization in standard-cell design”, in Design Automation Conference, 1990. Proceedings., 27th ACM/IEEE, 1990, pp. 349 -352.
N. Modi and Marek-Sadowska, M., “ECO-Map: Technology remapping for post-mask ECO using simulated annealing”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 652 -657.
Y. - L. Wu and Marek-Sadowska, M., “An efficient router for 2-D field programmable gate array”, in European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings., 1994, pp. 412 -416.
S. Lin and Marek-Sadowska, M., “A fast and efficient algorithm for determining fanout trees in large networks”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 539 -544.
T. Xiao and Marek-Sadowska, M., “Functional correlation analysis in crosstalk induced critical paths identification”, in Design Automation Conference, 2001. Proceedings, 2001, pp. 653 - 656.
F. Chen, Mittl, S., Shinosky, M., Swift, A., Kontra, R., Anderson, B., Aitken, J., Wang, Y., Kinser, E., Kumar, M., Wang, Y., Kane, T., Feng, K. D., Henson, W. K., Mocuta, D., and Li, Di-an, “Investigation of emerging middle-of-line poly gate-to-diffusion contact reliability issues”, in Reliability Physics Symposium (IRPS), 2012 IEEE International, 2012, pp. 6A.4.1 -6A.4.9.
M. - F. Hsiao, Marek-Sadowska, M., and Chen, S. - J., “Minimizing coupling jitter by buffer resizing for coupled clock networks”, in Circuits and Systems, 2003. ISCAS '03. Proceedings of the 2003 International Symposium on, 2003, vol. 5, p. V-509 - V-512 vol.5.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., “Modeling crosstalk in resistive VLSI interconnections”, in VLSI Design, 1999. Proceedings. Twelfth International Conference On, 1999, pp. 470 -475.
B. Hu and Marek-Sadowska, M., “Multilevel expansion-based VLSI placement with blockages”, in Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on, 2004, pp. 558-564.
W. Maly, Yi-Wei Lin, and Marek-Sadowska, M., “OPC-Free and Minimally Irregular IC Design Style”, in Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 2007, pp. 954 -957.
S. Lin, Marek-Sadowska, M., and Kuh, E. S., “SWEC: a stepwise equivalent conductance timing simulator for CMOS VLSI circuits”, in Design Automation. EDAC., Proceedings of the European Conference on, 1991, pp. 142 -148.
S. - H. Weng, Kuo, Y. - M., Chang, S. - C., and Marek-Sadowska, M., “Timing analysis considering IR drop waveforms in power gating designs”, in Computer Design, 2008. ICCD 2008. IEEE International Conference on, 2008, pp. 532 -537.
B. Chen and Marek-Sadowska, M., “Timing driven placement of pads and latches”, in ASIC Conference and Exhibit, 1992., Proceedings of Fifth Annual IEEE International, 1992, pp. 30 -33.
A. Mukherjee, Marek-Sadowska, M., and Long, S. I., “Wave pipelining YADDs-a feasibility study”, in Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999, 1999, pp. 559 -562.
Journal Article
L. H. Chen, Marek-Sadowska, M., and Brewer, F., “Buffer delay change in the presence of power and ground noise”, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 11, pp. 461 -473, 2003.
A. Vittal, Chen, L. H., Marek-Sadowska, M., Wang, K. - P., and Yang, S., “Crosstalk in VLSI interconnections”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 1817 -1824, 1999.
A. Vittal and Marek-Sadowska, M., “Crosstalk reduction for VLSI”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 16, pp. 290 -298, 1997.
Y. Ran, Kondratyev, A., Tseng, K., Watanabe, Y., and Marek-Sadowska, M., “Eliminating false positives in crosstalk noise analysis”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 24, pp. 1406 - 1419, 2005.
D. I. Cheng, Cheng, K. - T., Wang, D. C., and Marek-Sadowska, M., “A hybrid methodology for switching activities estimation”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 17, pp. 357 -366, 1998.
C. - C. Lin, Chen, K. - C., and Marek-Sadowska, M., “Logic synthesis for engineering change”, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 18, pp. 282 -292, 1999.

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